From 1b6a04ca5504955c571d1c97504fb45ea0befee4 Mon Sep 17 00:00:00 2001
From: Valentin Popov <valentin@popov.link>
Date: Mon, 8 Jan 2024 01:21:28 +0400
Subject: Initial vendor packages

Signed-off-by: Valentin Popov <valentin@popov.link>
---
 vendor/zeroize/src/aarch64.rs | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 vendor/zeroize/src/aarch64.rs

(limited to 'vendor/zeroize/src/aarch64.rs')

diff --git a/vendor/zeroize/src/aarch64.rs b/vendor/zeroize/src/aarch64.rs
new file mode 100644
index 0000000..07744d0
--- /dev/null
+++ b/vendor/zeroize/src/aarch64.rs
@@ -0,0 +1,35 @@
+//! [`Zeroize`] impls for ARM64 SIMD registers.
+//!
+//! Gated behind the `aarch64` feature: MSRV 1.59
+//! (the overall crate is MSRV 1.60)
+
+use crate::{atomic_fence, volatile_write, Zeroize};
+
+use core::arch::aarch64::*;
+
+macro_rules! impl_zeroize_for_simd_register {
+    ($($type:ty),* $(,)?) => {
+        $(
+            #[cfg_attr(docsrs, doc(cfg(target_arch = "aarch64")))]
+            impl Zeroize for $type {
+                #[inline]
+                fn zeroize(&mut self) {
+                    volatile_write(self, unsafe { core::mem::zeroed() });
+                    atomic_fence();
+                }
+            }
+        )+
+    };
+}
+
+// TODO(tarcieri): other NEON register types?
+impl_zeroize_for_simd_register! {
+    uint8x8_t,
+    uint8x16_t,
+    uint16x4_t,
+    uint16x8_t,
+    uint32x2_t,
+    uint32x4_t,
+    uint64x1_t,
+    uint64x2_t,
+}
-- 
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