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author | Valentin Popov <valentin@popov.link> | 2024-07-19 15:37:58 +0300 |
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committer | Valentin Popov <valentin@popov.link> | 2024-07-19 15:37:58 +0300 |
commit | a990de90fe41456a23e58bd087d2f107d321f3a1 (patch) | |
tree | 15afc392522a9e85dc3332235e311b7d39352ea9 /vendor/portable-atomic/src/imp/interrupt/riscv.rs | |
parent | 3d48cd3f81164bbfc1a755dc1d4a9a02f98c8ddd (diff) | |
download | fparkan-a990de90fe41456a23e58bd087d2f107d321f3a1.tar.xz fparkan-a990de90fe41456a23e58bd087d2f107d321f3a1.zip |
Deleted vendor folder
Diffstat (limited to 'vendor/portable-atomic/src/imp/interrupt/riscv.rs')
-rw-r--r-- | vendor/portable-atomic/src/imp/interrupt/riscv.rs | 81 |
1 files changed, 0 insertions, 81 deletions
diff --git a/vendor/portable-atomic/src/imp/interrupt/riscv.rs b/vendor/portable-atomic/src/imp/interrupt/riscv.rs deleted file mode 100644 index 65b1af2..0000000 --- a/vendor/portable-atomic/src/imp/interrupt/riscv.rs +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: Apache-2.0 OR MIT - -// Refs: -// - https://five-embeddev.com/riscv-isa-manual/latest/machine.html#machine-status-registers-mstatus-and-mstatush -// - https://five-embeddev.com/riscv-isa-manual/latest/supervisor.html#sstatus -// -// Generated asm: -// - riscv64gc https://godbolt.org/z/osbzsT679 - -#[cfg(not(portable_atomic_no_asm))] -use core::arch::asm; - -pub(super) use super::super::riscv as atomic; - -// Status register -#[cfg(not(portable_atomic_s_mode))] -macro_rules! status { - () => { - "mstatus" - }; -} -#[cfg(portable_atomic_s_mode)] -macro_rules! status { - () => { - "sstatus" - }; -} - -// MIE (Machine Interrupt Enable) bit (1 << 3) -#[cfg(not(portable_atomic_s_mode))] -const MASK: State = 0x8; -#[cfg(not(portable_atomic_s_mode))] -macro_rules! mask { - () => { - "0x8" - }; -} -// SIE (Supervisor Interrupt Enable) bit (1 << 1) -#[cfg(portable_atomic_s_mode)] -const MASK: State = 0x2; -#[cfg(portable_atomic_s_mode)] -macro_rules! mask { - () => { - "0x2" - }; -} - -#[cfg(target_arch = "riscv32")] -pub(super) type State = u32; -#[cfg(target_arch = "riscv64")] -pub(super) type State = u64; - -/// Disables interrupts and returns the previous interrupt state. -#[inline] -pub(super) fn disable() -> State { - let r: State; - // SAFETY: reading mstatus and disabling interrupts is safe. - // (see module-level comments of interrupt/mod.rs on the safety of using privileged instructions) - unsafe { - // Do not use `nomem` and `readonly` because prevent subsequent memory accesses from being reordered before interrupts are disabled. - asm!(concat!("csrrci {0}, ", status!(), ", ", mask!()), out(reg) r, options(nostack, preserves_flags)); - } - r -} - -/// Restores the previous interrupt state. -/// -/// # Safety -/// -/// The state must be the one retrieved by the previous `disable`. -#[inline] -pub(super) unsafe fn restore(r: State) { - if r & MASK != 0 { - // SAFETY: the caller must guarantee that the state was retrieved by the previous `disable`, - // and we've checked that interrupts were enabled before disabling interrupts. - unsafe { - // Do not use `nomem` and `readonly` because prevent preceding memory accesses from being reordered after interrupts are enabled. - asm!(concat!("csrsi ", status!(), ", ", mask!()), options(nostack, preserves_flags)); - } - } -} |