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| author | Georgiy Bondarenko <69736697+nehilo@users.noreply.github.com> | 2021-03-04 20:54:23 +0300 |
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| committer | Georgiy Bondarenko <69736697+nehilo@users.noreply.github.com> | 2021-03-04 20:54:23 +0300 |
| commit | e8701195e66f2d27ffe17fb514eae8173795aaf7 (patch) | |
| tree | 9f519c4abf6556b9ae7190a6210d87ead1dfadde /buildroot/share/PlatformIO/variants/CHITU_F103/variant.h | |
| download | kp3s-lgvl-e8701195e66f2d27ffe17fb514eae8173795aaf7.tar.xz kp3s-lgvl-e8701195e66f2d27ffe17fb514eae8173795aaf7.zip | |
Initial commit
Diffstat (limited to 'buildroot/share/PlatformIO/variants/CHITU_F103/variant.h')
| -rw-r--r-- | buildroot/share/PlatformIO/variants/CHITU_F103/variant.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/buildroot/share/PlatformIO/variants/CHITU_F103/variant.h b/buildroot/share/PlatformIO/variants/CHITU_F103/variant.h new file mode 100644 index 0000000..cd10bb3 --- /dev/null +++ b/buildroot/share/PlatformIO/variants/CHITU_F103/variant.h @@ -0,0 +1,17 @@ +#pragma once + +#define digitalPinToPort(P) ( PIN_MAP[P].gpio_device ) +#define digitalPinToBitMask(P) ( BIT(PIN_MAP[P].gpio_bit) ) +#define portOutputRegister(port) ( &(port->regs->ODR) ) +#define portInputRegister(port) ( &(port->regs->IDR) ) + +#define portSetRegister(pin) ( &(PIN_MAP[pin].gpio_device->regs->BSRR) ) +#define portClearRegister(pin) ( &(PIN_MAP[pin].gpio_device->regs->BRR) ) + +#define portConfigRegister(pin) ( &(PIN_MAP[pin].gpio_device->regs->CRL) ) + +static const uint8_t SS = BOARD_SPI1_NSS_PIN; +static const uint8_t SS1 = BOARD_SPI2_NSS_PIN; +static const uint8_t MOSI = BOARD_SPI1_MOSI_PIN; +static const uint8_t MISO = BOARD_SPI1_MISO_PIN; +static const uint8_t SCK = BOARD_SPI1_SCK_PIN; |