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author | Valentin Popov <valentin@popov.link> | 2024-01-08 00:21:28 +0300 |
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committer | Valentin Popov <valentin@popov.link> | 2024-01-08 00:21:28 +0300 |
commit | 1b6a04ca5504955c571d1c97504fb45ea0befee4 (patch) | |
tree | 7579f518b23313e8a9748a88ab6173d5e030b227 /vendor/zeroize/src/aarch64.rs | |
parent | 5ecd8cf2cba827454317368b68571df0d13d7842 (diff) | |
download | fparkan-1b6a04ca5504955c571d1c97504fb45ea0befee4.tar.xz fparkan-1b6a04ca5504955c571d1c97504fb45ea0befee4.zip |
Initial vendor packages
Signed-off-by: Valentin Popov <valentin@popov.link>
Diffstat (limited to 'vendor/zeroize/src/aarch64.rs')
-rw-r--r-- | vendor/zeroize/src/aarch64.rs | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/vendor/zeroize/src/aarch64.rs b/vendor/zeroize/src/aarch64.rs new file mode 100644 index 0000000..07744d0 --- /dev/null +++ b/vendor/zeroize/src/aarch64.rs @@ -0,0 +1,35 @@ +//! [`Zeroize`] impls for ARM64 SIMD registers. +//! +//! Gated behind the `aarch64` feature: MSRV 1.59 +//! (the overall crate is MSRV 1.60) + +use crate::{atomic_fence, volatile_write, Zeroize}; + +use core::arch::aarch64::*; + +macro_rules! impl_zeroize_for_simd_register { + ($($type:ty),* $(,)?) => { + $( + #[cfg_attr(docsrs, doc(cfg(target_arch = "aarch64")))] + impl Zeroize for $type { + #[inline] + fn zeroize(&mut self) { + volatile_write(self, unsafe { core::mem::zeroed() }); + atomic_fence(); + } + } + )+ + }; +} + +// TODO(tarcieri): other NEON register types? +impl_zeroize_for_simd_register! { + uint8x8_t, + uint8x16_t, + uint16x4_t, + uint16x8_t, + uint32x2_t, + uint32x4_t, + uint64x1_t, + uint64x2_t, +} |